1. Field of the Invention
The present invention relates to configurations of semiconductor integrated circuit devices, and more particularly, to a circuit configuration for a testing operation of a semiconductor integrated circuit device including a memory circuit.
2. Description of the Background Art
Due to the progress in miniaturization techniques in recent years, semiconductor memories, such as a dynamic random access memory (hereinafter, referred to as "DRAM"), have increasingly larger capacities. As the number of bits per chip has increased, the time required for the test has been lengthened. This has increased the cost for the test, and the reduction of the test time has become an important issue in the production of the semiconductor memories.
Increasing the number of semiconductor memory device chips that can be tested at one time (hereinafter, referred to a "batch count") leads to reduction in the test time per chip, which may lower the test cost.
Generally, an effort to increase the batch count, however, requires an investment for a tester device, and therefore, such increase in the batch count would not necessarily lead to the reduction in the test cost.
Now, a configuration and an operation of a tester which can test a plurality of conventional semiconductor memory devices at the same time will be described in brief.
FIG. 13 is a schematic diagram illustrating connection of a conventional tester 8000 and an m number (m is a natural number) of semiconductor memory devices 8010.1-8010.m that are simultaneously tested by tester 8000.
Semiconductor memory devices 8010.i (i is a natural number; 1.ltoreq.i .ltoreq.m) has external pins as follows:
(1) a power supply pin for providing power necessary for the operation of semiconductor memory device 8010.i; PA1 (2) an address pin for input of an address for designation of an address within a memory region to semiconductor memory device 8010.i; PA1 (3) a control pin for control of an operating mode of semiconductor memory device 8010.i; and PA1 (4) a data input/output pin for input/output of data when reading/writing data stored in semiconductor memory device 8010.i.
When testing a plurality of semiconductor memory devices 8010.1-8010.m at the same time, a common operating condition and an identical address for reading/writing can be used for them. Thus, of the above-described pins of semiconductor memory devices 8010.1-8010.m, (1) the power supply pins, (2) the address pins and (3) the control pins of the corresponding devices can be connected to common lines to receive the same signals from tester 8000, so that the relevant pins are short-circuited with one another.
Conversely, (4) the data input/output pin of each device should be monitored independently, to determine soundness thereof. Thus, tester 8000 generally has a configuration in which an output from each of semiconductor memory devices 8010.1-8010.m can be taken in separately.
Specifically, if each of semiconductor memory devices 8010.1-8010.m has an input/output bus width of 16 bits, tester 8000 should have 16.times.m data input/output terminals such that data can be input to or output from the respective 16.times.m input/output pins. In addition, tester 8000 should have a configuration allowing the m number of chip select signals to be output so that semiconductor memory devices 8010.1-8010.m can be selected independent of one another.
Therefore, in the case where semiconductor memory devices 8010.1-8010.m each having an input/output bus width of 16 bits are being measured at the same time, if the batch count is incremented by 1, the number of pins of tester 8000 should be increased by 16, and a configuration permitting the output of another chip select signal is required.
Specifically, a driving circuit for driving a pin as well as a comparison circuit for determining whether data output from semiconductor memory device 8010.1-80180.m are sound or not, should be added for every pin increased in tester 8000. Thus, the cost required for increasing the batch count becomes enormous.
Another kind of tester for testing a plurality of semiconductor memory devices 8010.1-8010.m in a batch is a burn-in tester performing a so-called burn-in test.
FIG. 14 is a schematic diagram illustrating connection in the case where such a burn-in tester 9000 is used for simultaneous measurement of an m number of semiconductor memory devices 8010.1-8010.m.
Here, burn-in tester 9000 is normally known as a low-cost test device with a large batch count.
The burn-in tester is a tester for detection of defective products, which operates semiconductor memory devices 8010.1-8010.m continuously under more stressful conditions (with a higher operating power supply voltage and a higher operating environmental temperature) than normal operating conditions for a long period of time.
In other words, the primary role in the burn-in tester is to cause semiconductor memory devices 8010.1-8010.m to operate continuously for a long period of time to reveal the presence of an initial defect. Thus, the corresponding input/output pins of respective chips are short-circuited, and therefore, the number of pins required for the burn-in tester is far less than that for general tester 8000.
Specifically, for the configuration of burn-in tester 9000, the data input/output pins corresponding to semiconductor memory devices 8010.1-8010.m are short-circuited and connected to tester 9000. Thus, even if the number of semiconductor memory devices to be measured at the same time increases, the number of data input/output terminals required for tester 9000 remains unchanged; i.e., it remains 16 if the semiconductor memory device has a data input/output bus width of 16 bits.
Accordingly, burn-in tester 9000 is more cost effective than general tester 8000 when they have the same batch count.
If the batch count increases, it is necessary to provide semiconductor memory devices 8010.0-8010.m. with the chip select signals (one ICS for each chip), but their input/output data pins may be short-circuited, as described above. Therefore, what is required for the increase in the batch count, is only to increase the number of pins according to the increment in the number of chips. Thus, it is easier for tester 9000 to increase the batch count than for the general test device 8000.
Here, however, the input/output data pins of the semiconductor memory devices are short-circuited. Therefore, if the condition of each chip is to be examined, it is necessary to select the chips, one chip at a time, and to selectively read out data from the selected semiconductor memory device 8010.i. Thus, of the pins of the simultaneously measured semiconductor memory devices 8010.1-8010.m, those for receiving chip select signals /CS cannot be short-circuited with one another.
The operating mode as described above in which chips are selected one by one for reading out data, is herein called a "scan mode".
If semiconductor memory devices 8010.1-8010.m can be tested using low-cost burn-in test 9000, the cost for testing the semiconductor memory devices would be reduced. However, with the conventional semiconductor memory devices 8010.1-8010.m, it has been difficult to test the multiple devices in batches, due to the following reasons.
As described above, in the combination of conventional burn-in tester 9000 and conventional semiconductor memory devices 8010.1-8010.m, the complementary bus inserted between the memory cell and the output buffer is equalized every time the data are read out, whereby the preceding read data are lost. Thus, even if burn-in tester 9000 performs the test programs for a plurality of chips at the same time, for the determination of pass/fail of each chip, data read out from semiconductor memory devices 8010.1-8010.m according to the execution of the test programs should be compared with an expected value one by one.
In addition, because of the specific connection for burn-in tester 9000 in which input/output pins of the plurality of semiconductor memory devices 8010.1-8010.m are being short-circuited, the data reading is only effected for one semiconductor memory device 8010.i at a time, selected by activation of a corresponding chip select signal. Therefore, to read out data from semiconductor memory devices 8010.1-8010.m during the execution of the test programs, each of semiconductor memory devices 8010.1-8010.m should be selected one by one for the data reading, every time the address changes. This has made the simultaneous measurement of multiple devices by the burn-in tester impractical.
In the above description, the semiconductor memory device, especially a DRAM, has been mentioned by way of example. However, the similar problems arise when a semiconductor integrated circuit device incorporating a semiconductor memory device and a logic circuit is being tested.